This invention relates to a memory used in a packet switching network and, more particularly, to a packet transmission memory for storing and outputting data bits through a data conversion between a serial data and a parallel data and a method used therein.
A packet switching network is used in an information store and forward exchanging service. A piece of information to be transmitted is divided into plural data blocks, and an address representative of the destination is added to each of the plural data blocks. Each data block and the address are stored in a packet, and the packets are transmitted through the packet switching network to the destination.
In the packet switching network, the communication lines are shared among plural terminals, and, accordingly, the packet forming a part of the piece of information concurrently flows through the communication lines together with packets forming parts of other pieces of information. In order to prevent a packet from concurrent occupation with another packet, the packets are temporarily stored in a memory, and are read out from the memory at an appropriate timing. The packet is transferred through the packet switching network in the form of a serial bit string, and is stored at a data storage region in the memory in the form of parallel bits. The memory is hereinbelow referred to as xe2x80x9cpacket transmission memoryxe2x80x9d.
A typical example of the packet transmission memory has plural addressable data storage regions, and 512 bits are storable in each of the addressable data storage regions. The packet or the serial bit string is supplied to the data input port of the packet transmission memory, and is stored in one of the addressable data storage regions. A serial-to-parallel data conversion is required for the packet transmission memory.
A packet transmission memory is disclosed in Japanese Patent Application laid-open No. 6-266638. The prior art packet transmission memory internally converts a digital data signal between serial bits and parallel bits. FIG. 1 shows the prior art packet transmission memory disclosed in the Japanese Patent Application laid-open. The prior art packet transmission memory 6 is integrated on a semiconductor chip, and is connected between a communication network 200 and a MCU (Micro Controller Unit) 7. The prior art packet transmission memory 6 comprises a main controlling circuit 61, an 8-bit configuration RAM (Random Access Memory) block 62, a counter 63, a signal reception controller 64, a signal transmission controller 65, a data register 66 and an address register 67. The main controlling circuit 61 supervises the RAM 62, the signal reception controller 64 and the signal transmission controller 65, and controls data write-in operation/data read-out operation on the RAM 62, a data reception from the network 200 and a data transmission to the network 200.
Though not shown in FIG. 1, the RAM 62 includes a memory cell array, a read-out shift register and a write-in shift register. The memory cells are arranged into plural rows. The read-out shift register has a data storage capacity equal to the row of memory cells, and the write-in shift register also has the data storage capacity equal to the row of memory cells. A digital data signal representative of a piece of write-in data is supplied in serial from the signal reception controller 64 to the write-in shift register, and the data bits of the digital data signal are successively stored in the write-in shift register. When one of the rows of memory cells is selected from the memory cell array, the stored data bits are output in parallel from the write-in shift register to the selected row of memory cells, and are stored therein. When the piece of data is accessed, the data bits are read out in parallel from the row of memory cells to the read-out shift register, and are concurrently stored in the read-out shift register. The data bits are serially supplied from the read-out shift register to the signal transmission controller 65.
A problem is encountered in that the RAM 62 consumes a wide real estate on the semiconductor chip.
It is therefore an important object of the present invention to provide a packet transmission memory which is integrated on a relatively narrow real estate on a semiconductor chip.
To accomplish the object, the present invention proposes to directly write serial data bits in an addressable data storage region of a memory.
In accordance with one aspect of the present invention, there is provided a memory for readably storing data bits of packets therein comprising plural addressable data storage regions each having plural memory cells, a data distributing circuit connected to the plural addressable data storage regions and responsive to an internal address signal selectively specifying the plural memory cells of an addressable data storage region selected from the plural addressable data storage regions for providing a data path to the memory cell specified by the internal bit address signal, a data write-in unit responsive to an external address signal for selectively enabling the plural addressable data storage regions and successively transferring the data bits of a received packet to the data distributing circuit, an internal address generator synchronously cooperating with the data write-in unit for supplying the internal address signal to the data distributing circuit, and a parallel-to-serial converter connected to the plural addressable data storage regions, storing the data bits read out from an addressable data storage region selected from the plural addressable data storage regions, and serially outputting the data bits to the outside.
In accordance with another aspect of the present invention, there is provided a method for writing data bits of a packet in and reading out the data bits from a data storage region having memory cells of a memory, and the method comprises the steps of a) selecting the data storage region from the memory, b) receiving the first data bit of the packet, c) providing a data path to one of the memory cells of the data storage region for storing the first data bit in the aforesaid one of the memory cells, d) receiving the next data bit of the packet, e) changing the data path from the aforesaid one of the memory cells to another of the memory cells for storing the next data bit in the aforesaid another of the memory cells, f) repeating the steps d) and e) until the last data bit is stored in a memory cell of the data storage region, g) concurrently reading out the data bits of the packet from the memory cells of the data storage region, h) storing the data bits in a parallel-to-serial converter and i) serially outputting the data bits from the parallel-to-serial converter.